1. Field of the Invention
The present invention relates generally to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device and a manufacturing method thereof which are suitable for a non-volatile memory such as a NAND type EEPROM, etc., in which an element isolation insulation film is embedded after depositing a gate electrode.
2. Description of the Background Art
An STI (Shallow Trench Isolation) technique has hitherto been known as an element isolation technique used for a high-integration memory such as a NAND type EEPROM, etc. The STI technique is that a shallow trench is formed in an element isolation region on a semiconductor substrate, and the shallow trench is filled with an element isolation insulation material.
The followings are specific methods to which the STI technique is applied:
(a) An element isolation insulation film is formed by embedding then a gate insulation layer and a gate electrode are sequentially formed in a device region.
(b) A gate insulation layer and a gate electrode layer are sequentially formed for on the entire substrate, then the gate electrode layer, the gate insulation layer and the substrate are etched to dig a trench, then an insulating material is filled in the trench.
FIG. 1A is a plan view of a memory cell array area of the NAND type EEPROM, showing a state where the element isolation insulation film is embedded by applying the latter method, and FIG. 1B is a sectional view taken along the line A-A' thereof. shown in FIGS. 1A and 1B, before embedding an element isolation insulation film 4, a gate electrode 6 serving as a part of a floating gate electrode and a silicon nitride layer 7 serving as a stopper mask material for a CMP process, are deposited on a silicon substrate 1 through a gate insulation film (tunnel insulation film) 5. The silicon nitride layer 7, the gate electrode 6, the gate insulation film 5 and the substrate 1 are etched by RIE (Reactive Ion Etching) using a resist pattern, thereby forming a trench 3 in an element isolation region. The element isolation insulation film 4 is embedded in the trench 3. A striped device area 2 defined by the element isolation insulation film 4 is thereby provided. The element isolation insulation film 4 is embedded substantially flush with the silicon nitride layer 7, hereafter, the silicon nitride layer 7 is removed, and a control gate electrode is provided by stacking it.
FIG. 2A is a plan view showing a state where a control gate electrode 9 is formed in on pattern, and FIG. 2B is a sectional view taken along the line B-B' thereof. At a stage shown in FIG. 1B, the gate electrode 6 has been isolated, however, the isolation per memory transistor within the striped device area 2 is not yet done. After removing the silicon nitride layer 7, a gate electrode 6b composing a floating gate electrode is deposited together with the gate electrode 6, and a slit is formed in an element isolation region. Thereafter, an inter-layer gate insulting layer 8 is provided thereon, and a control gate electrode 9 is provided. In a process of patterning the control gate electrode 9, simultaneously the gate electrodes 6b,6 are etched, thereby obtaining a floating gate electrode isolated per memory transistor in the device area 2.
According to the conventional manufacturing method, however, as shown in FIG. 2A, etching residuals 10 of the gate electrodes 6, 6b are produced along the boundary of the element isolation trench 3 between the patterned control gate electrodes 9. This is because if the element isolation insulation film 4 is as shown in FIG. 1B embedded in the trench formed by the RIE, the element isolation insulation film 4 takes, when removing the silicon nitride layer 7 thereafter, such a form of protruding in an inverted tapered shape above the gate electrode 6.
Namely, when patterning the control gate electrode 9 and subsequently etching the gate electrodes 6b, 6 in sequence, of the gate electrodes 6b, 6, especially the lower gate electrode 6, of which some areas are shadowed by corners of the element isolation insulation film 4, is not therefore completely etched. These etching residuals 10 might cause a defect such as a floating gate short-circuit of the memory transistor in the NAND type cell.
The same kind of problem might occur in not only the NAND type EEPROM but also other types of transistor circuits using the similar element isolation technique.